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FEATURES
2 (R)
Ne Tolew 5V Inp rant 22Luts on V10 D
GAL22LV10
Low Voltage E2CMOS PLD Generic Array LogicTM
FUNCTIONAL BLOCK DIAGRAM
I/CLK
RESET
* HIGH PERFORMANCE E CMOS TECHNOLOGY -- 4 ns Maximum Propagation Delay -- Fmax = 250 MHz -- 3 ns Maximum from Clock Input to Data Output -- UltraMOS(R) Advanced CMOS Technology * 3.3V LOW VOLTAGE 22V10 ARCHITECTURE -- JEDEC-Compatible 3.3V Interface Standard -- 5V Compatible Inputs -- I/O Interfaces with Standard 5V TTL Devices (GAL22LV10C) * ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D) * E2 CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention * TEN OUTPUT LOGIC MACROCELLS -- Maximum Flexibility for Complex Logic Designs -- Programmable Output Polarity * PRELOAD AND POWER-ON RESET OF ALL REGISTERS -- 100% Functional Testability * APPLICATIONS INCLUDE: -- Glue Logic for 3.3V Systems -- DMA Control -- State Machine Control -- High Speed Graphics Processing -- Standard Logic Speed Upgrade * ELECTRONIC SIGNATURE FOR IDENTIFICATION DESCRIPTION The GAL22LV10D, at 4 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL22LV10C can interface with both 3.3V and 5V signal levels. The GAL22LV10 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
8 OLMC
I/O/Q
I
10 OLMC
I
12
I/O/Q
I
OLMC
I/O/Q
PROGRAMMABLE AND-ARRAY (132X44)
14 OLMC
I
I/O/Q
16 OLMC
I
I/O/Q
I
16 OLMC
I/O/Q
I
14 OLMC
I/O/Q
I
12 OLMC
I/O/Q
I
10 OLMC
I/O/Q
I
8 OLMC
I/O/Q
I
PRESET
PIN CONFIGURATION
PLCC
I/CLK I/O/Q Vcc NC I/O/Q 26 25 I/O/Q I/O/Q 7 23
I 4 I I I NC I I I 11 12 I 9 5
I
2
28
GAL22LV10
Top View
I/O/Q NC
21
I/O/Q I/O/Q
14 I GND NC
16 I I/O/Q
19 18 I/O/Q
I/O/Q
Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
22lv10_03
1
Specifications GAL22LV10
GAL22LV10 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns) 4 5 7.5 10 15 Tsu (ns) 3 3.5 6.5 7.5 10 Tco (ns) 3 3.5 5 6.5 10 Icc (mA) 130 130 75 75 75 Ordering # GAL22LV10D-4LJ GAL22LV10D-5LJ GAL22LV10C-7LJ GAL22LV10C-10LJ GAL22LV10C-15LJ Package 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC
PART NUMBER DESCRIPTION
XXXXXXXX _ XX X XX
GAL22LV10D Device Name GAL22LV10C Speed (ns) L = Low Power Power Grade Blank = Commercial
Package J = PLCC
2
Specifications GAL22LV10
OUTPUT LOGIC MACROCELL (OLMC)
The GAL22LV10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two OLMCs have sixteen product terms (pins 21 and 23). In addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. The GAL22LV10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen.
AR
D Q CLK SP Q
4 TO 1 MUX
2 TO 1 MUX
GAL22LV10 OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
Each of the Macrocells of the GAL22LV10 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC's D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop's /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either "on" (dedicated output), "off" (dedicated input), or "productterm driven" (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array.
3
Specifications GAL22LV10
REGISTERED MODE
AR
AR
D
Q
D
Q
CLK SP
Q
CLK SP
Q
ACTIVE LOW S0 = 0 S1 = 0 S0 = 1 S1 = 0
ACTIVE HIGH
COMBINATORIAL MODE
ACTIVE LOW S0 = 0 S1 = 1 S0 = 1 S1 = 1
ACTIVE HIGH
4
Specifications GAL22LV10
GAL22LV10 LOGIC DIAGRAM / JEDEC FUSE MAP
PLCC Package Pinout
2
0
0000 0044 . . . 0396
4
8
12
16
20
24
28
32
36
40
ASYNCHRONOUS RESET (TO ALL REGISTERS)
8
OLMC
S0 5808 S1 5809
27
0440 . . . . 0880
10
OLMC
S0 5810 S1 5811
26
3
0924 . . . . . 1452
12
OLMC
S0 5812 S1 5813
25
4
1496 . . . . . . 2112
14
OLMC
S0 5814 S1 5815
24
5
2156 . . . . . . . 2860
16
OLMC
S0 5816 S1 5817
23
6
2904 . . . . . . . 3608
16
OLMC
S0 5818 S1 5819
21
7
3652 . . . . . . 4268
14
OLMC
S0 5820 S1 5821
20
9
4312 . . . . . 4840
12
OLMC
S0 5822 S1 5823
19
10
4884 . . . . 5324
10
OLMC
S0 5824 S1 5825
18
11
5368 . . . 5720
8
OLMC
S0 5826 S1 5827
17
12
5764
13
5828, 5829 ...
M S B L S B
SYNCHRONOUS PRESET (TO ALL REGISTERS)
16
Electronic Signature
... 5890, 5891
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
5
Specifications GAL22LV10D Specifications GAL22LV10
ABSOLUTE MAXIMUM RATINGS(1)
Supply voltage VCC .................................... -0.5 to +4.6V Input voltage applied ................................. -0.5 to +5.6V I/O voltage applied .................................... -0.5 to +4.6V Off-state output voltage applied................. -0.5 to +4.6V Storage Temperature .................................. -65 to 150C Ambient Temperature with Power Applied ......................................... -55 to 125C
1.Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
RECOMMENDED OPERATING COND.
Commercial Devices: Ambient Temperature (TA) ............................... 0 to 75C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage I/O High Voltage CONDITION MIN. Vss - 0.3 2.0 2.0 0V VIN VIL (MAX.) (Vcc-0.2)V VIN VCC Vcc VIN 5.25V Vcc VIN 4.6V IOL = MAX. Vin = VIL or VIH IOL = 500A Vin = VIL or VIH -- -- -- -- -- -- 2.4 Vcc-0.2V -- -- VCC = 3.3V VOUT = 0.5V TA= 25C -15 TYP.3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- MAX. 0.8 5.25 Vcc+0.5 -100 10 10 20 0.4 0.2 -- -- 8 -8 -80 UNITS V V V A A A mA V V V V mA mA mA
VIL VIH IIL1 IIH
Input or I/O Low Leakage Current Input or I/O High Leakage Current Input High Leakage Current I/O High Leakage Current
VOL VOH IOL IOH IOS2
Output Low Voltage
Output High Voltage
IOH = MAX. Vin = VIL or VIH IOH = -100A Vin = VIL or VIH
Low Level Output Current High Level Output Current Output Short Circuit Current
COMMERCIAL ICC Operating Power
Supply Current
VIL = 0V
VIH = 3.0V Unused Inputs at VIL
--
90
130
mA
ftoggle = 1MHz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 3.3V and TA = 25 C
6
Specifications GAL22LV10D Specifications GAL22LV10
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
COM PARAMETER COM
TEST COND1. A A -- -- -- A
DESCRIPTION Input or I/O to Combinational Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Feedback before Clock Hold Time, Input or Feedback after Clock Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled Input or I/O to Output Disabled Input or I/O to Asynchronous Reset of Register Asynchronous Reset Pulse Duration Asynchronous Reset to Clock Recovery Time Synchronous Preset to Clock Recovery Time 1 1 -- 3 0
-4
-5 UNITS
MIN. MAX. MIN. MAX.
tpd2 tco2 tcf3 tsu th
4 3 2.5 -- -- --
1 1 -- 3.5 0 143
5 3.5 3 -- -- --
ns ns ns ns ns MHz
167
fmax4
A A
182 250
-- --
154 200
-- --
MHz MHz
twh4 twl4 ten tdis tar tarw tarr tspr
1) 2) 3) 4)
-- -- B C A -- -- --
2 2 1 1 1 4.5 3.5 3.5
-- -- 5 5 4.5 -- -- --
2.5 2.5 1 1 1 5.5 4 4
-- -- 6 6 5.5 -- -- --
ns ns ns ns ns ns ns ns
Refer to Switching Test Conditions section. Minimum values for tpd and tco are not 100% tested but established by characterization. Calculated from fmax with internal feedback. Refer to fmax Descriptions section. Refer to fmax Descriptions section. Characterized but not 100% tested.
CAPACITANCE (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance TYPICAL 5 5 UNITS pF pF TEST CONDITIONS VCC = 3.3V, VI = 0V VCC = 3.3V, VI/O = 0V
7
Specifications GAL22LV10C Specifications GAL22LV10
ABSOLUTE MAXIMUM RATINGS(1)
Supply voltage VCC .................................... -0.5 to +5.6V Input voltage applied ................................. -0.5 to +5.6V Off-state output voltage applied................. -0.5 to +5.6V Storage Temperature.................................. -65 to 150C Ambient Temperature with Power Applied ......................................... -55 to 125C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
RECOMMENDED OPERATING COND.
Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current 0V VIN VIL (MAX.) (VCC - 0.2)V VIN VCC VCC VIN 5.25V CONDITION MIN.
Vss - 0.5
TYP.2 -- -- -- -- -- -- -- -- -- -- -- -- --
MAX. 0.8 5.25
UNITS V V A A mA V V V V V mA mA mA
VIL VIH IIL IIH VOL VOH
2.0 -- -- -- -- -- 2.4 Vcc-0.45 Vcc-0.2 -- -- VCC = 3.3V VOUT = 0.5V TA = 25C -15
-10
10 30 0.4 0.2 -- -- -- 8 -4 -60
Output Low Voltage
IOL = MAX. Vin = VIL or VIH IOL = 0.5 mA Vin = VIL or VIH
Output High Voltage
IOH = MAX. Vin = VIL or VIH IOH = -0.5 mA Vin = VIL or VIH IOH = -100 A Vin = VIL or VIH
IOL IOH IOS1
Low Level Output Current High Level Output Current Output Short Circuit Current
COMMERCIAL ICC Operating Power
Supply Current
VIL = 0.0V VIH = 3.0V ftoggle = 1MHz Outputs Open
--
45
75
mA
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 3.3V and TA = 25 C
8
Specifications GAL22LV10C Specifications GAL22LV10
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
COM PARAM TEST COND.1 COM COM
DESCRIPTION Input or I/O to Combinatorial Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Fdbk before Clk Hold Time, Input or Fdbk after Clk Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled Input or I/O to Output Disabled Input or I/O to Asynch. Reset of Reg. Asynch. Reset Pulse Duration Asynch. Reset to Clk Recovery Time Synch. Preset to Clk Recovery Time 2 1 -- 6.5 0 87
-7
-10
-15 UNITS ns ns ns ns ns MHz
MIN. MAX. MIN. MAX. MIN. MAX. 7.5 5 3 -- -- -- 2 1 -- 7.5 0 71 10 6.5 5 -- -- -- 2 1 -- 10 0 50 15 10 5 -- -- --
tpd2 tco2 tcf3 tsu th
A A -- -- -- A
fmax4
A A
105 125
-- --
80 111
-- --
66 83
-- --
MHz MHz
twh twl ten tdis tar tarw tarr tspr
-- -- B C A -- -- --
3.5 3.5 2 2 2 7 7 8
-- -- 10 10 11 -- -- --
4 4 2 2 2 8 8 10
-- -- 12 12 13 -- -- --
6 6 2 2 2 12 10 10
-- -- 15 15 20 -- -- --
ns ns ns ns ns ns ns ns
1) Refer to Switching Test Conditions section. 2) Minimum values for tpd and tco are not 100% tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Description section. 4) Refer to fmax Description section.
CAPACITANCE (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance TYPICAL 8 8 UNITS pF pF TEST CONDITIONS VCC = 3.3V, VI = 0V VCC = 3.3V, VI/O = 0V
9
Specifications GAL22LV10
SWITCHING WAVEFORMS
INPUT or I/O FEEDBACK
INPUT or I/O FEEDBACK
VALID INPUT
VALID INPUT
tpd
COMBINATORIAL OUTPUT
ts u
CLK
th
tc o
Combinatorial Output
REGISTERED OUTPUT
1/
fm a x
(external fdbk)
Registered Output
INPUT or I/O FEEDBACK
tdis
OUTPUT
ten
CLK
1/
fm a x
(int ern al fd bk )
Input or I/O to Output Enable/Disable
REGISTERED FEEDBACK
tc f
tsu
fmax with Feedback
tw h
CLK
1/
tw l
fm a x
(w/o fdbk)
Clock Width
INPUT or I/O FEEDBACK DRIVING SP CLK
INPUT or I/O FEEDB ACK DRIVI NG AR
tsu
th
tspr
CLK
tarw
tco
REGISTERED OUTPUT
R E G I S T ER E D OUTPUT
tarr
tar
Synchronous Preset Asynchronous Reset
10
Specifications GAL22LV10
fmax DESCRIPTIONS
CLK
LOGIC ARRAY
REGISTER
CLK
LOGIC ARRAY
tsu
tco
REGISTER
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
CLK
tcf tpd
LOGIC ARRAY
fmax with Internal Feedback 1/(tsu+tcf)
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
11
Specifications GAL22LV10
GAL22LV10D: SWITCHING TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load Output Load Conditions (see figure) Test Condition A B C High Z to Active High at 1.9V High Z to Active Low at 1.0V Active High to High Z at 1.9V Active Low to High Z at 1.0V R1 50 50 50 50 50 CL 35pF 35pF 35pF 35pF 35pF
FROM OUTPUT (O/Q) UNDER TEST Z0 = 50, CL = 35pF*
GND to 3.0V 1.5ns 10% - 90% 1.5V 1.5V See Figure
TEST POINT R1 +1.45V
*CL includes test fixture and probe capacitance.
GAL22LV10C: SWITCHING TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 2.0ns 10% - 90% 1.5V 1.5V See Figure
FROM OUTPUT (O/Q) UNDER TEST TEST POINT R1 +3.3V
3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition A B C Active High Active Low Active High Active Low R1 316 316 316 316 316 R2 348 348 348 348 348 CL 35pF 35pF 35pF 5pF 5pF
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
12
Specifications GAL22LV10
ELECTRONIC SIGNATURE
An electronic signature (ES) is provided in every GAL22LV10 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. The electronic signature is an additional feature not present in other manufacturers' 22V10 devices. To use the extra feature of the user-programmable electronic signature it is necessary to choose a Lattice Semiconductor 22V10 device type when compiling a set of logic equations. In addition, many device programmers have two separate selections for the device, typically a GAL22LV10 and a GAL22V10-UES (UES = User Electronic Signature) or GAL22V10-ES. This allows users to maintain compatibility with existing 22V10 designs, while still having the option to use the GAL device's extra feature. The JEDEC map for the GAL22LV10 contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. However, the GAL22LV10 device can still be programmed with a standard 22V10 JEDEC map (5828 fuses) with any qualified device programmer.
OUTPUT REGISTER PRELOAD
When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The GAL22LV10 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically.
INPUT BUFFERS
GAL22LV10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The input and I/O pins on the GAL22LV10D also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. (See equivalent input and I/O schematics on the following page.) Typical Input Pull-up Characteristic
0 -10
Input Current (A)
SECURITY CELL
A security cell is provided in every GAL22LV10 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.
LATCH-UP PROTECTION
GAL22LV10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch.
-20 -30 -40 -50 -60 -70 -80
0 1 2 3 0.5 1.5 2.5
DEVICE PROGRAMMING
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
Input Voltage (V)
13
3.5
4
Specifications GAL22LV10
POWER-UP RESET
Vcc Vcc (min.)
tsu
CLK
twl tpr
INTERNAL REGISTER Q - OUTPUT
Internal Register Reset to Logic "0"
ACTIVE LOW OUTPUT REGISTER
Device Pin Reset to Logic "1"
ACTIVE HIGH OUTPUT REGISTER
Device Pin Reset to Logic "0"
Circuitry within the GAL22V10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the asyn-
chronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL22V10. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN
Feedback PIN
Vcc
Active Pull-up Circuit (GAL22LV10D Only)
Active Pull-up Circuit (GAL22LV10D Only) Tri-State Control Vcc Vref
Vcc
ESD Protection Circuit
Vref
Vcc
PIN
Data Output
PIN
ESD Protection Circuit
Typ. Vref = Vcc Typical Input
Typ. Vref = Vcc
Feedback (To Input Buffer)
Typical Output
14
Specifications GAL22LV10
GAL22LV10D: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
1.2 1.05
Normalized Tco vs Vcc
1.2
Normalized Tsu vs Vcc
Normalized Tpd
Normalized Tco
1.1
Normalized Tsu
PT H->L PT L->H
1
RISE 1.025 FALL
PT H->L
1.1
PT L->H
1
1
0.9
0.975
0.9
0.8 3.00
3.15
3.30
3.45
3.60
0.95 3.00
3.15
3.30
3.45
3.60
0.8 3.00
3.15
3.30
3.45
3.60
Supply Voltage (V) Normalized Tpd vs Temp
1.3 1.3
Supply Voltage (V) Normalized Tco vs Temp
1.4
Supply Voltage (V) Normalized Tsu vs Temp
Normalized Tpd
Normalized Tco
Normalized Tsu
1.2 1.1 1 0.9 0.8 0.7 -55
PT H->L PT L->H
1.2 1.1 1 0.9 0.8 0.7 -55
RISE FALL
1.3 1.2 1.1 1 0.9 0.8 0.7
PT H->L PT L->H
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
-55
-25
0
25
50
75
100
125
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching
0 0
Delta Tco vs # of Outputs Switching
Delta Tpd (ns)
Delta Tco (ns)
-0.1 -0.2 -0.3 -0.4 -0.5 1 2 3
RISE FALL
-0.1 -0.2 -0.3 -0.4 -0.5
RISE FALL
1 2 3 4 5 6 7 8 9 10
4
5
6
7
8
9
10
Number of Outputs Switching Delta Tpd vs Output Loading
20 16 20
Number of Outputs Switching Delta Tco vs Output Loading
RISE FALL
Delta Tpd (ns)
12 8 4 0 -4 -8 0 50
Delta Tco (ns)
16 12 8 4 0 -4
RISE FALL
100
150
200
250
300
0
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
15
Specifications GAL22LV10
GAL22LV10D: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
1 0.8 4
Voh vs Ioh
3.1
Voh vs Ioh
3
3
Voh (V)
0.6 0.4 0.2 0 0.00 5.00 10.00 15.00 20.00 25.00 30.00
2
Voh (V)
5.00 10.00 15.00 20.00
Vol (V)
2.9
1
2.8
0 0.00
2.7 0.00 1.00 2.00 3.00 4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.40 1.3
Normalized Icc vs Temp
1.30
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
1.20
1.1 1 0.9 0.8 0.7
Normalized Icc
-55 -25 0 25 50 75 100 125
1.2
1.25 1.20 1.15 1.10 1.05 1.00 0 25 50 75 100
1.00
0.80
0.60 3.00
3.15
3.30
3.45
3.60
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
7 6 0 5 10
Input Clamp (Vik)
Delta Icc (mA)
5 4 3 2 1 0 0.00
Iik (mA)
0.50 1.00 1.50 2.00 2.50 3.00 3.50
15 20 25 30 35 -2.00
-1.50
-1.00
-0.50
0.00
Vin (V)
Vik (V)
16
Specifications GAL22LV10
GAL22LV10C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
1.2 1.05
Normalized Tco vs Vcc
1.2
Normalized Tsu vs Vcc
Normalized Tpd
Normalized Tco
1.1
Normalized Tsu
PT H->L PT L->H
1
RISE 1.025 FALL
PT H->L
1.1
PT L->H
1
1
0.9
0.975
0.9
0.8 3.00 3.15 3.30 3.45 3.60
0.95 3.00 3.15 3.30 3.45 3.60
0.8 3.00 3.15 3.30 3.45 3.60
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.3 1.3
Normalized Tco vs Temp
1.4
Normalized Tsu vs Temp
Normalized Tpd
Normalized Tco
Normalized Tsu
1.2 1.1 1 0.9 0.8 0.7 -55 -25
PT H->L PT L->H
1.2 1.1 1 0.9 0.8 0.7
RISE FALL
1.3 1.2 1.1 1 0.9 0.8 0.7
PT H->L PT L->H
0
25
50
75
100
125
-55
-25
0
25
50
75
100
125
-55
-25
0
25
50
75
100
125
Temperature (deg. C) Delta Tpd vs # of Outputs Switching
0
Temperature (deg. C) Delta Tco vs # of Outputs Switching
0
Temperature (deg. C)
Delta Tpd (ns)
-0.2 -0.3 -0.4 -0.5 1 2 3 4 5 6 7 8 9 10
Delta Tco (ns)
-0.1
-0.1 -0.2 -0.3 -0.4 -0.5 1 2 3 4 5 6 7 8 9 10
RISE FALL
RISE FALL
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
28 24 26
Delta Tco vs Output Loading
RISE
22
RISE FALL
Delta Tpd (ns)
Delta Tco (ns)
20 16 12 8 4 0 -4 -8 0 50 100 150 200 250 300
FALL
18 14 10 6 2 -2 -6 0 50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
17
Specifications GAL22LV10
GAL22LV10C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
1 0.8 4
Voh vs Ioh
3.1
Voh vs Ioh
3
3
Voh (V)
0.6 0.4 0.2 0 0.00
2
Voh (V)
5.00 10.00 15.00 20.00
Vol (V)
2.9
1
2.8
10.00
20.00
30.00
40.00
0 0.00
2.7 0.00
1.00
2.00
3.00
4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.40 1.2
Normalized Icc vs Temp
1.80
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
1.20
1.1
Normalized Icc
-55 -25 0 25 50 75 100 125
1.60 1.40 1.20 1.00 0.80 0 25 50 75 100
1.00
1
0.80
0.9
0.60 3.00 3.15 3.30 3.45 3.60
0.8
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
5 4 3 2 1 0 0.00 0 10
Input Clamp (Vik)
Delta Icc (mA)
Iik (mA)
20 30 40 50 60 -2.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
-1.50
-1.00
-0.50
0.00
Vin (V)
Vik (V)
18

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